In a long postscript to 65816: Build 4 – Adding Expanded RAM I discussed some alternatives I tried to achieve the following memory map in my ATF22V10C PLD. There’s nothing magical about this memory map, it’s just something I wanted to try, for reasons I’ll discuss in a operating system post if I ever get …
65816: Build 4 – Adding Expanded RAM
I’ve mentioned previously having trouble getting WINCUPL to create the following memory map: I figured that since I was expanding ROM, I might as well give myself a full 32k of RAM. WINCUPL didn’t like that though, giving me an error that it didn’t have enough pterms for my ROM_CS pin. I took the easy …
65816: Build 4 – Current Status – 7/15/2022
Build 4 – Current Specification As of 7/15/2022, Build 4 has tested successfully with: Both 65C02 and 65C816 up to 10 MHz where I started to get display glitches 524k memory. Current configuration: ~457k RAM ($0000-$F7FF, $20000-$7FFFF), 55 ns ~67k ROM ($F800-$1FEFF), 70 ns 256 bytes I/O ($1FF00-$1FFFF) 65C22 VIA ($1FF10, shift register dedicated to …
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65816: Build 4 – Troubleshooting 4 – Testing a Different Address Decoder
Off and on throughout my Build 4 troubleshooting journey I kept wondering if the PLD was the underlying issue. While a PLD is handy for making after the fact changes to your build’s memory map, it also has a handy feature I hadn’t thought of before. Since the PLD brings control input and output signals …
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6502: My Fourth Build – Testing the New Programmable Logic Device
I completed my fourth 6502 build the other day. It’s a barebones build, mainly intended to test my new PLD-based address decoding/interrupt request design. I didn’t need serial or keyboard support to test the PLD so haven’t included quite a bit of the I/O support that I had in build 3. I’m thinking that I’ll …
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6502: Programmable Logic Devices – Address Decoder Revisited
I mentioned in my last post, Venturing Forth, that I ordered a programmable logic device to better refine my address decoding as my current circuit wastes about 16k on I/O. I worked up the new memory map and PLD files while waiting for the device to arrive. Then, as seems all too common with me, …
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6502: My Third Build
With my second build, I’d successfully tested the hardware, memory and I/O devices I wanted to use in my third build, my planned handheld unit. Eager to move on, I quickly drew up a schematic and laid out a PCB for my planned design. Consistent with a handheld unit, I wanted to keep the PCB …
6502: Memory
My first 6502 build, which followed Ben Eater’s 6502 computer project, uses two pretty pedestrian memory chips, an Atmel AT28C256 32k byte EEPROM and a 62256 32k byte SRAM. The EEPROM has a relatively slow 150 nanosecond access time. The SRAM access time is faster at 70 nanoseconds. The significance of these access times become …
6502: Memory Map and Address Decoder
The 6502 microprocessor can address a 64k byte range. As a system designer you must split this address space between RAM, ROM and I/O according to your requirements. My first 6502 build, which followed Ben Eater’s 6502 computer project, used a straight forward memory map with 16k bytes of RAM (address range $0000-$3FFF), 32k bytes …