I completed my fourth 6502 build the other day. It’s a barebones build, mainly intended to test my new PLD-based address decoding/interrupt request design. I didn’t need serial or keyboard support to test the PLD so haven’t included quite a bit of the I/O support that I had in build 3. I’m thinking that I’ll …
Continue reading “6502: My Fourth Build – Testing the New Programmable Logic Device”
This is a work in progress, documenting my findings related to my 65816 build. Its rough, intending to get my findings written down before I forget them. I’ll hopefully be able to polish it as I go along. In this post I am documenting various signals in the Western Design Center’s W65C816SXB Development Board. I’ll …
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I mentioned in my last post, Venturing Forth, that I ordered a programmable logic device to better refine my address decoding as my current circuit wastes about 16k on I/O. I worked up the new memory map and PLD files while waiting for the device to arrive. Then, as seems all too common with me, …
Continue reading “6502: Programmable Logic Devices – Address Decoder Revisited”
My first 6502 build, which followed Ben Eater’s 6502 computer project, uses two pretty pedestrian memory chips, an Atmel AT28C256 32k byte EEPROM and a 62256 32k byte SRAM. The EEPROM has a relatively slow 150 nanosecond access time. The SRAM access time is faster at 70 nanoseconds. The significance of these access times become …
The 6502 microprocessor can address a 64k byte range. As a system designer you must split this address space between RAM, ROM and I/O according to your requirements. My first 6502 build, which followed Ben Eater’s 6502 computer project, used a straight forward memory map with 16k bytes of RAM (address range $0000-$3FFF), 32k bytes …