In a long postscript to 65816: Build 4 – Adding Expanded RAM I discussed some alternatives I tried to achieve the following memory map in my ATF22V10C PLD. There’s nothing magical about this memory map, it’s just something I wanted to try, for reasons I’ll discuss in a operating system post if I ever get …
65816: Build 4 – Adding Expanded RAM
I’ve mentioned previously having trouble getting WINCUPL to create the following memory map: I figured that since I was expanding ROM, I might as well give myself a full 32k of RAM. WINCUPL didn’t like that though, giving me an error that it didn’t have enough pterms for my ROM_CS pin. I took the easy …
65816: Build 4 – Current Status – 7/15/2022
Build 4 – Current Specification As of 7/15/2022, Build 4 has tested successfully with: Both 65C02 and 65C816 up to 10 MHz where I started to get display glitches 524k memory. Current configuration: ~457k RAM ($0000-$F7FF, $20000-$7FFFF), 55 ns ~67k ROM ($F800-$1FEFF), 70 ns 256 bytes I/O ($1FF00-$1FFFF) 65C22 VIA ($1FF10, shift register dedicated to …
Continue reading “65816: Build 4 – Current Status – 7/15/2022”
65816: Build 4 Troubleshooting 1 – It’s the PLD, or is it?
I worked on the Build 4 modifications over several weeks, partly because I was just playing around with what I had on hand when I started and partly getting sidetracked looking into why things happen instead of just getting on with the build. In this post I discuss one of those side investigations regarding the …
Continue reading “65816: Build 4 Troubleshooting 1 – It’s the PLD, or is it?”
6502: My Fourth Build – Testing the New Programmable Logic Device
I completed my fourth 6502 build the other day. It’s a barebones build, mainly intended to test my new PLD-based address decoding/interrupt request design. I didn’t need serial or keyboard support to test the PLD so haven’t included quite a bit of the I/O support that I had in build 3. I’m thinking that I’ll …
Continue reading “6502: My Fourth Build – Testing the New Programmable Logic Device”
6502: Programmable Logic Devices – Address Decoder Revisited
I mentioned in my last post, Venturing Forth, that I ordered a programmable logic device to better refine my address decoding as my current circuit wastes about 16k on I/O. I worked up the new memory map and PLD files while waiting for the device to arrive. Then, as seems all too common with me, …
Continue reading “6502: Programmable Logic Devices – Address Decoder Revisited”