Build 4 – Current Specification As of 7/15/2022, Build 4 has tested successfully with: Both 65C02 and 65C816 up to 10 MHz where I started to get display glitches 524k memory. Current configuration: ~457k RAM ($0000-$F7FF, $20000-$7FFFF), 55 ns ~67k ROM ($F800-$1FEFF), 70 ns 256 bytes I/O ($1FF00-$1FFFF) 65C22 VIA ($1FF10, shift register dedicated to …
Continue reading “65816: Build 4 – Current Status – 7/15/2022”
Off and on throughout my Build 4 troubleshooting journey I kept wondering if the PLD was the underlying issue. While a PLD is handy for making after the fact changes to your build’s memory map, it also has a handy feature I hadn’t thought of before. Since the PLD brings control input and output signals …
Continue reading “65816: Build 4 – Troubleshooting 4 – Testing a Different Address Decoder”
I left Build 4 successfully running with the 65816 and 55 ns RAM. But it failed with memory corruption when I used 12 ns RAM. The problem was that occasionally during RAM writes, some address signals would change about 2 ns before the write enable signal would rise. This would result in a write to …
Continue reading “65816: Troubleshooting 3 – Revisiting the Build 4 Layout”
I worked on the Build 4 modifications over several weeks, partly because I was just playing around with what I had on hand when I started and partly getting sidetracked looking into why things happen instead of just getting on with the build. In this post I discuss troubleshooting the memory corruption issues I found. …
Continue reading “65816: Build 4 Troubleshooting 2 – Memory Corruption”
I worked on the Build 4 modifications over several weeks, partly because I was just playing around with what I had on hand when I started and partly getting sidetracked looking into why things happen instead of just getting on with the build. In this post I discuss one of those side investigations regarding the …
Continue reading “65816: Build 4 Troubleshooting 1 – It’s the PLD, or is it?”
I worked on the Build 4 modifications over several weeks, partly because I was just playing around with what I had on hand when I started and partly getting sidetracked looking into why things happen instead of just getting on with the build. In this post, I discuss modifying Build 4 in more detail. In …
Continue reading “65816: Modifying Build 4 as a 65816 Testbed”
I had just finished building and testing my fourth 6502 build, a barebones testbed for my new PLD based address decoder. With my PLD successfully tested, the build didn’t really have much use anymore, except testing new PLD designs in the future. Given that it was barebones I figured it would be fun to see …
Continue reading “6502/65816: Running a 6502 build with a 65816”
I ran into an interesting problem the other day trying to upgrade my 6502 build 4 to work with the 65816. I plan to write more on this in another post, but after just one minor change I got build 4 with a 65816 to almost startup my 6502-based Forth operating system. For some reason, …
Continue reading “6502: Coding – Just because it works doesn’t mean it’s correct”
This is a work in progress, documenting my findings related to my 65816 build. Its rough, intending to get my findings written down before I forget them. I’ll hopefully be able to polish it as I go along. In this post I am documenting various signals in the Western Design Center’s W65C816SXB Development Board. I’ll …
Continue reading “65816: Exploring the W65C816SXB Development Board”