I left Build 4 successfully running with the 65816 and 55 ns RAM. But it failed with memory corruption when I used 12 ns RAM. The problem was that occasionally during RAM writes, some address signals would change about 2 ns before the write enable signal would rise. This would result in a write to …
Continue reading “65816: Troubleshooting 3 – Revisiting the Build 4 Layout”
I worked on the Build 4 modifications over several weeks, partly because I was just playing around with what I had on hand when I started and partly getting sidetracked looking into why things happen instead of just getting on with the build. In this post I discuss troubleshooting the memory corruption issues I found. …
Continue reading “65816: Build 4 Troubleshooting 2 – Memory Corruption”
I worked on the Build 4 modifications over several weeks, partly because I was just playing around with what I had on hand when I started and partly getting sidetracked looking into why things happen instead of just getting on with the build. In this post I discuss one of those side investigations regarding the …
Continue reading “65816: Build 4 Troubleshooting 1 – It’s the PLD, or is it?”
I worked on the Build 4 modifications over several weeks, partly because I was just playing around with what I had on hand when I started and partly getting sidetracked looking into why things happen instead of just getting on with the build. In this post, I discuss modifying Build 4 in more detail. In …
Continue reading “65816: Modifying Build 4 as a 65816 Testbed”
I had just finished building and testing my fourth 6502 build, a barebones testbed for my new PLD based address decoder. With my PLD successfully tested, the build didn’t really have much use anymore, except testing new PLD designs in the future. Given that it was barebones I figured it would be fun to see …
Continue reading “6502/65816: Running a 6502 build with a 65816”
I ran into an interesting problem the other day trying to upgrade my 6502 build 4 to work with the 65816. I plan to write more on this in another post, but after just one minor change I got build 4 with a 65816 to almost startup my 6502-based Forth operating system. For some reason, …
Continue reading “6502: Coding – Just because it works doesn’t mean it’s correct”
I completed my fourth 6502 build the other day. It’s a barebones build, mainly intended to test my new PLD-based address decoding/interrupt request design. I didn’t need serial or keyboard support to test the PLD so haven’t included quite a bit of the I/O support that I had in build 3. I’m thinking that I’ll …
Continue reading “6502: My Fourth Build – Testing the New Programmable Logic Device”
This is a work in progress, documenting my findings related to my 65816 build. Its rough, intending to get my findings written down before I forget them. I’ll hopefully be able to polish it as I go along. In this post I am documenting various signals in the Western Design Center’s W65C816SXB Development Board. I’ll …
Continue reading “65816: Exploring the W65C816SXB Development Board”
I mentioned in my last post, Venturing Forth, that I ordered a programmable logic device to better refine my address decoding as my current circuit wastes about 16k on I/O. I worked up the new memory map and PLD files while waiting for the device to arrive. Then, as seems all too common with me, …
Continue reading “6502: Programmable Logic Devices – Address Decoder Revisited”
My daughters came home for the summer soon after my last post and as my work area is in their normally vacant bedroom, I chose to work more on the software side of things for the summer. Well, that turned into an adventure that’s kept me occupied for the last six months. They’ll be home …